cadence IC 5141安装总结（八）（图文教程）
1、下面是修改.bashrc文件
# .bashrc
# User specific aliases and functions
alias lmli='/home/eda/ic5141/tools/bin/lmgrd -c /home/eda/ic5141/share/license/license.dat'
alias openbook='CDS_ROOT/tools/dfII/bin/cdsdoc'
# Source global definitions
if [ -f /etc/bashrc ]; then
. /etc/bashrc
fi
export CDS_ROOT=/home/eda/ic5141
export CDS_LIC_FILE=5280@localhost
export LM_LICENSE_FILE=$CDS_ROOT/share/license/license.dat
export CDS_Netlisting_Mode=Analog
export PATH=$CDS_ROOT/tools/spectre/bin:$CDS_ROOT/tools/bin:$CDS_ROOT/tools/dfII/bin:$PATH
~
2、然后哦就 lmli
[redhat3@localhost redhat3]$ lmli
Incorrectly built binary which accesses errno or h_errno directly. Needs to be fixed.
[redhat3@localhost redhat3]$ 16:19:05 (lmgrd) -----------------------------------------------
16:19:05 (lmgrd) Please Note:
16:19:05 (lmgrd)
16:19:05 (lmgrd) This log is intended for debug purposes only.
16:19:05 (lmgrd) There are many details in licensing policies
16:19:05 (lmgrd) that are not reported in the information logged
16:19:05 (lmgrd) here, so if you use this log file for any kind
16:19:05 (lmgrd) of usage reporting you will generally produce
16:19:05 (lmgrd) incorrect results.
16:19:05 (lmgrd)
16:19:05 (lmgrd) -----------------------------------------------
16:19:05 (lmgrd)
16:19:05 (lmgrd)
16:19:05 (lmgrd) FLEXlm (v8.4a) started on localhost (linux) (2/2/2015)
16:19:05 (lmgrd) Copyright (c) 1988-2003 by Macrovision Corporation. All rights reserved.
16:19:05 (lmgrd) US Patents 5,390,297 and 5,671,412.
16:19:05 (lmgrd) World Wide Web: http://www.macrovision.com
16:19:05 (lmgrd) License file(s): /home/eda/ic5141/share/license/license.dat
16:19:05 (lmgrd) lmgrd tcp-port 5280
16:19:05 (lmgrd) Starting vendor daemons ...
16:19:05 (lmgrd) Started cdslmd (internet tcp_port 32781 pid 26823)
Incorrectly built binary which accesses errno or h_errno directly. Needs to be fixed.
16:19:05 (cdslmd) FLEXlm version 8.4a
16:19:05 (cdslmd) Server started on localhost for: 100
16:19:05 (cdslmd) 111 11400 12141
16:19:05 (cdslmd) 12500 14000 14010
16:19:05 (cdslmd) 14020 14040 14101
16:19:05 (cdslmd) 14111 14120 14130
16:19:05 (cdslmd) 14140 14410 200
16:19:05 (cdslmd) 20120 20121 20122
16:19:05 (cdslmd) 20123 20124 20127
16:19:05 (cdslmd) 20128 20220 20221
16:19:05 (cdslmd) 20222 20227 206
16:19:05 (cdslmd) 207 21060 21200
16:19:05 (cdslmd) 21400 21900 21920
16:19:05 (cdslmd) 22650 22800 22810
16:19:05 (cdslmd) 24015 24025 24100
16:19:05 (cdslmd) 24205 250 251
16:19:05 (cdslmd) 26000 274 276
16:19:05 (cdslmd) 279 283 300
16:19:05 (cdslmd) 305 312 314
16:19:05 (cdslmd) 316 318 32110
16:19:05 (cdslmd) 32140 32150 32190
16:19:05 (cdslmd) 322 32500 32501
16:19:05 (cdslmd) 32502 32510 32550
16:19:05 (cdslmd) 32600 32610 32620
16:19:05 (cdslmd) 32630 32640 32760
16:19:05 (cdslmd) 33010 33301 334
16:19:05 (cdslmd) 336 34500 34510
16:19:05 (cdslmd) 365 370 371
16:19:05 (cdslmd) 37100 373 40020
16:19:05 (cdslmd) 40030 40040 40500
16:19:05 (cdslmd) 41000 50000 50010
16:19:05 (cdslmd) 501 50110 50200
16:19:05 (cdslmd) 51022 51023 51060
16:19:05 (cdslmd) 51070 51170 550
16:19:05 (cdslmd) 570 61300 61400
16:19:05 (cdslmd) 71110 71120 71130
16:19:05 (cdslmd) 920 940 945
16:19:05 (cdslmd) 950 960 963
16:19:05 (cdslmd) 964 965 966
16:19:05 (cdslmd) 972 974 991
16:19:05 (cdslmd) 994 995 ABIT
16:19:05 (cdslmd) ALL_EBD AMD_MACH ANALOG_WORKBENCH
16:19:05 (cdslmd) AWB_BEHAVIOR AWB_Batch AWB_DIST_SIM
16:19:05 (cdslmd) AWB_MAGAZINE AWB_MAGNETICS AWB_MIX
16:19:05 (cdslmd) AWB_PPLOT AWB_RESOLVE_OPT AWB_SIMULATOR
16:19:05 (cdslmd) AWB_SMOKE AWB_SPICEPLUS AWB_STATS
16:19:05 (cdslmd) Actel_FPGA Advanced_Cell_Placer Advanced_Package_Designer
16:19:05 (cdslmd) Affirma_AMS_distrib_processing Affirma_NC_Simulator Affirma_NC_VHDL_Desktop_Sim
16:19:05 (cdslmd) Affirma_RF_IC_package Affirma_RF_SPW_model_link Affirma_advanced_analysis_env
16:19:05 (cdslmd) Affirma_equivalence_checker Affirma_sim_analysis_env Allegro_CAD_Interface
16:19:05 (cdslmd) Allegro_Designer Allegro_PCB_Interface Altera_MAX
16:19:05 (cdslmd) Ambit_BuildGates Ambit_libcompile Artist_Optimizer
16:19:05 (cdslmd) Artist_Statistics Atmel_ATV BOGUS
16:19:05 (cdslmd) Base_Digital_Body_Lib Base_Verilog_Lib BlockMaster_Characterizer
16:19:05 (cdslmd) BlockMaster_Optimizer BoardQuest_Team BuildGates_Extreme
16:19:05 (cdslmd) CELL3 CELL3_ARO CELL3_CROSSTALK
16:19:05 (cdslmd) CELL3_CTS CELL3_ECL CELL3_OPENDEV
16:19:05 (cdslmd) CELL3_OPENEXE CELL3_PA CELL3_PR
16:19:05 (cdslmd) CELL3_QPLACE_TIMING CELL3_SCAN CELL3_TIMING
16:19:05 (cdslmd) CELL3_WIDEWIRE CP_Ele_Checks CPtoolkit
16:19:05 (cdslmd) CWAVES CWB01 CWB03
16:19:05 (cdslmd) CWB04 CWB05 CheckPlus
16:19:05 (cdslmd) Clock_Tree_Generation Cobra_Simulator ComposerCheckPlus_AdvRules
16:19:05 (cdslmd) ComposerCheckPlus_Checker ComposerCheckPlus_RuleDev Composer_EDIF300_Connectivity
16:19:05 (cdslmd) Composer_EDIF300_Schematic Composer_Spectre_Sim_Solution ConcICe_Option
16:19:05 (cdslmd) Corners_Analysis DISCRETE_LIB DRAC2CORE
16:19:05 (cdslmd) DRAC2DRC DRAC2LVS DRAC3CORE
16:19:05 (cdslmd) DRAC3DRC DRAC3LVS DRACACCESS
16:19:05 (cdslmd) DRACDIST DRACERC DRACLPE
16:19:05 (cdslmd) DRACLVS DRACPG_E DRACPLOT
16:19:05 (cdslmd) DRACPRE DRACSLAVE Datapath_Preview_Option
16:19:05 (cdslmd) Datapath_VHDL Datapath_Verilog Device_Level_Placer
16:19:05 (cdslmd) Device_Level_Router Distributed_Dracula_Option EBD_edit
16:19:05 (cdslmd) EBD_floorplan EBD_power EDIF_Netlist_Interface
16:19:05 (cdslmd) EDIF_Schematic_Interface EMCdisplay EMControl
16:19:05 (cdslmd) Envisia_GE_ultra_place_route Envisia_PKS Envisia_RAC
16:19:05 (cdslmd) Envisia_Utility Envisia_LowPower_option Envisia_DataPath_option
16:19:05 (cdslmd) Envisia_SE_ultra_place_route Extended_Digital_Body_Lib Extended_Digital_Lib
16:19:05 (cdslmd) Extended_Verilog_Lib FPGA_Flows FPGA_OPTIMIZER
16:19:05 (cdslmd) FPGA_Tools FUNCTION_LIB Framework
16:19:05 (cdslmd) GATEENSEMBLE GATEENSEMBLE_ARO GATEENSEMBLE_CROSSTALK
16:19:05 (cdslmd) GATEENSEMBLE_CTS GATEENSEMBLE_CTS_LE GATEENSEMBLE_CTS_UL
16:19:05 (cdslmd) GATEENSEMBLE_ECL GATEENSEMBLE_LOWEND GATEENSEMBLE_OPENDEV
16:19:05 (cdslmd) GATEENSEMBLE_OPENEXE GATEENSEMBLE_PA GATEENSEMBLE_PR_LE
16:19:05 (cdslmd) GATEENSEMBLE_PR_UL GATEENSEMBLE_QPLACE_TIMING GATEENSEMBLE_SCAN
16:19:05 (cdslmd) GATEENSEMBLE_TIMING GATEENSEMBLE_TIMING_LE GATEENSEMBLE_TIMING_UL
16:19:05 (cdslmd) GATEENSEMBLE_UNLIMITED GATEENSEMBLE_WIDEWIRE Gate_Ensemble_DSM
16:19:05 (cdslmd) Gate_Ensemble_DSM_Crosstalk Gate_Ensemble_WARP HDL-DESKTOP
16:19:05 (cdslmd) IC_Inspector IC_autoroute IC_edit
16:19:05 (cdslmd) IC_hsrules IDF_Bi_Directional_Interface LAS_Cell_Optimization
16:19:05 (cdslmd) LEAPFROG-BV LEAPFROG-CV LEAPFROG-SLAVE
16:19:05 (cdslmd) LEAPFROG-SV LEAPFROG-SYS LID10
16:19:05 (cdslmd) LID11 LINEAR_LIB LSE
16:19:05 (cdslmd) MAG_LIB MIXAD_LIB Model_Check_Analysis
16:19:05 (cdslmd) NCSim_Desktop NCVLOG_CGOPTS NC_Verilog_Compiler
16:19:05 (cdslmd) NC_Verilog_Data_Prep_Compiler NC_Verilog_Simulator NC_VHDL_Simulator
16:19:05 (cdslmd) NC-simulator Nihongoconcept OASIS_Simulation_Interface
16:19:05 (cdslmd) OpenModeler_SFI OpenModeler_SWIFT OpenSim
16:19:05 (cdslmd) OpenWaves PICDesigner PIC_Utilities
16:19:05 (cdslmd) PLD PWM_LIB Pearl
16:19:05 (cdslmd) Pearl_Cell Placement_Based_Synthesis Prevail_Board_Designer
16:19:05 (cdslmd) Prevail_Correct_By_Design Prevail_Designer Preview_Synopsys_Interface
16:19:05 (cdslmd) QPlace Quickturn_Model_Manager RapidPART
16:19:05 (cdslmd) SWIFT Schematic_Generator SigNoiseCS
16:19:05 (cdslmd) SigNoiseEngineer SigNoiseExpert SigNoiseStdDigLib
16:19:05 (cdslmd) Signal_Integrity SiliconQuest SiliconQuest_CTGen_Option
16:19:05 (cdslmd) Silicon_Ensemble Silicon_Ensemble_CTS Silicon_Ensemble_DSM
16:19:05 (cdslmd) Silicon_Ensemble_DSM_Crosstalk Silicon_Ensemble_OpenDev Silicon_Ensemble_OpenExe
16:19:05 (cdslmd) Silicon_Ensemble_WARP Silicon_Synthesis_QPBS SimControl
16:19:05 (cdslmd) SimVision SpectreBasic SpectreRF
16:19:05 (cdslmd) Spectre_BTAHVMOS_Models Spectre_BTASOI_Models Spectre_NorTel_Models
16:19:05 (cdslmd) Spectre_ST_Models Substrate_Coupling_Analysis Synlink_Interface
16:19:05 (cdslmd) UET ULMdelta ULMecho
16:19:05 (cdslmd) ULMhotel ULMindia ULMjuliette
16:19:05 (cdslmd) ULMmike Universal_Smartpath VERILOG-SLAVE
16:19:05 (cdslmd) VERILOG-XL VERITIME VHDLLink
16:19:05 (cdslmd) VHDL_desktop VXL-ALPHA VXL-LMC-HW-IF
16:19:05 (cdslmd) VXL-SWITCH-RC VXL-TURBO VXL-VCW
16:19:05 (cdslmd) VXL-VET VXL-VLS VXL-VRA
16:19:05 (cdslmd) Vampire_HDRC Vampire_HLVS Vampire_MP
16:19:05 (cdslmd) Vampire_RCX Vampire_UI Verif_Ckpit_Analysis_Env
16:19:05 (cdslmd) Verilog_XL_Turbo_NT Verilog_XL_Desktop Verilog_desktop
16:19:05 (cdslmd) Virtuoso_Schem_Option Virtuoso_XL Xilinx_FPGA
16:19:05 (cdslmd) a2dxf aae-signalscan aae-signalscan-transaction
16:19:05 (cdslmd) aae-transaction-explorer actomd affirma-signalscan
16:19:05 (cdslmd) affirma-signalscan-control affirma-signalscan-pro affirma-signalscan-schmatic
16:19:05 (cdslmd) affirma-signalscan-source affirma-signalscan-transaction affirma-transaction-explorer
16:19:05 (cdslmd) allegro_dfa allegro_dfa_att allegro_non_partner
16:19:05 (cdslmd) allegro_symbol allegroprance archiver
16:19:05 (cdslmd) arouter caeviews cals_out
16:19:05 (cdslmd) catia cbds_in cdxe_in
16:19:05 (cdslmd) comp compose compose_autoplan
16:19:05 (cdslmd) compose_gcr compose_scells compose_tlmr
16:19:05 (cdslmd) compose_util concept conceptXPC
16:19:05 (cdslmd) cpe cpte crefer
16:19:05 (cdslmd) cvtomd debug dfsverifault
16:19:05 (cdslmd) dracula_in dxf2a e2v
16:19:05 (cdslmd) edif2ged expgen fethman
16:19:05 (cdslmd) fetsetup fluke fsim
16:19:05 (cdslmd) gbom ged2edif glib
16:19:05 (cdslmd) gloss gphysdly gscald
16:19:05 (cdslmd) gspares hp3070 iges_electrical
16:19:05 (cdslmd) intrgloss intrroute intrsignoise
16:19:05 (cdslmd) ipc_in ipc_out lwb
16:19:05 (cdslmd) mdin mdout mdtoac
16:19:05 (cdslmd) mdtocv multiwire packager
16:19:05 (cdslmd) pcb_editor pcb_engineer pcb_interactive
16:19:05 (cdslmd) pcb_prep pcb_review pcomp
16:19:05 (cdslmd) placement plotVersa ptc_in
16:19:05 (cdslmd) ptc_out quanticout redifnet
16:19:05 (cdslmd) rt sdrc_in sdrc_out
16:19:05 (cdslmd) signoise skillDev stream_in
16:19:05 (cdslmd) stream_out swap sx
16:19:05 (cdslmd) synSmartIF synSmartLib synTiOpt
16:19:05 (cdslmd) tsTSynVHDL tsTSynVLOG tsTestGen
16:19:05 (cdslmd) tsTestIntf tune tw01
16:19:05 (cdslmd) tw02 v2e vc-signalscan
16:19:05 (cdslmd) vc-signalscan-transaction vc-transaction-explorer verifault
16:19:05 (cdslmd) vgen viable visula_in
16:19:05 (cdslmd) vloglink wedifsch xilCds
16:19:05 (cdslmd) xilComposerFE xilConceptFE xilEdif
16:19:05 (cdslmd) TimingAnalysis RCExtraction DelayCal
16:19:05 (cdslmd) TrialRoute AmoebaPlace DesignViewer
16:19:05 (cdslmd) Route CeltIC SignalIntegrity
16:19:05 (cdslmd) ClockSyn PowerAnalysis SpecialRoute
16:19:05 (cdslmd) TimingBudget PartitionOptimizer FirstEncounter
16:19:05 (cdslmd) FirstEncounterSOC FE_Classic FE_Ultra
16:19:05 (cdslmd) SOC_Encounter Encounter_C Envisia_SE_SI_place_route
16:19:05 (cdslmd) NanoRoute_Ultra Nano_Encounter Multithread_Route_Option
16:19:05 (cdslmd) Cierto_SPW_comm_library_fxp_pt Cierto_HW_design_sys_2000 Cierto_SPW_multimedia_kit
16:19:05 (cdslmd) Cierto_SPW_GSM_VE Cierto_SPW_IS136_VE Cierto_SPW_pcscdma_VE
16:19:05 (cdslmd) Cierto_signal_proc_wrksys_2000 Cierto_SPW_comm_lib_flt_pt SPW_Smart_Antenna_Library
16:19:05 (cdslmd) Cierto_Wireless_LAN_Library Cierto_SPW_CDMA_Library Cierto_SPW_model_manager
16:19:05 (cdslmd)
16:19:05 (cdslmd) All FEATURE lines for this vendor behave like INCREMENT lines
16:19:05 (cdslmd)
3、上图已经说明license也是正确的，然后输入icfb&就可以顺利地满意地打开IC5141了。
4、下图是IC5141的新特性，不需要了解的话就可以关闭，其实每个cadence打开时都会跳出这样的界面，都可以关闭掉。
5、下图是开始建立一个新库的界面。和IC610是有点差别的。
6、下面就可以任意的画你的逻辑图了，记住前提是你必须加载你自己所需要的工艺库，不过这里加载库的确比IC610方便多了。
